1. Field of the Invention
The present disclosure relates to a method of forming a semiconductor device and to a method of forming a CMOS device and, more particularly, to forming CMOS devices in accordance with STI structures at advanced technology nodes.
2. Description of the Related Art
For next generation technologies, SOI (semiconductor-on-isolator) technology is an attractive candidate to push forward the frontiers imposed by Moore's law. Particularly, fully depleted SOI (FDSOI) techniques seem to provide promising technologies that allow the fabrication of semiconductor devices at technology nodes of 28 nm and beyond. Aside from FDSOI techniques allowing the combination of high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques, the fabrication processes, as employed in FDSOI techniques, are comparatively simple and actually represent a low risk evolution of conventional planar bulk CMOS techniques.
In general, a MOSFET as fabricated by SOI techniques is a semiconductor device (MOSFET) in which a semiconductor layer, such as silicon, germanium or silicon-germanium, is formed on a buried oxide (BOX) layer, which is in turn formed on a semiconductor substrate. Conventionally, there are two types of SOI devices: PDSOI (partially depleted SOI) and FDSOI MOSFETs. For example, in an N-type PDSOI MOSFET, a P-type film being sandwiched between a gate oxide (GOX) and a buried oxide (BOX) is so large that the depletion region cannot cover the whole vertical thickness of the P-region. Therefore, to some extent, PDSOI devices behave like bulk MOSFETs. In contrast, in an FDSOI device, the depletion region covers the whole vertical thickness of the semiconductor layer. As the gate insulation layer in FDSOI techniques supports fewer depletion charges than the bulk, an increase in inversion charges occurs in the fully depleted semiconductor layer, resulting in higher switching speeds. Therefore, FDSOI is considered as a promising candidate for fabricating MOSFET devices at advanced technology nodes of 28 nm and beyond, such as 20 nm and beyond.
A further approach for improving the performance of semiconductor devices employs strained silicon-germanium which enhances the mobility of holes in channels of PMOS devices, for example. In conventional FDSOI techniques, silicon-germanium is deposited before shallow trench isolation (STI) structures are formed in order to provide a silicon-germanium layer of good uniformity on the SOI wafer such that a particular stressor level is provided. It turns out that the particular stressor level of the deposited silicon-germanium layer, however, cannot be maintained throughout the processing and significant loss of stress is observed in fabricated CMOS devices.
In view of the above, it is desirable to provide a semiconductor device and a CMOS device at advanced technology nodes without losing the benefit of applying silicon-germanium layers as stressors for enhancing mobility in PMOS devices.